{ OnSiRoC II Sequencer code for DMILL APC steering with Decoder chip }

{ 	X = 29
	Y = 30
	Z = 31
	
	'ppcf': based on 'ppc1', but faster: only 14*48ns readout, less time for 
	specials
	
	use fast sequencer clock for Decoder loading
  	use FAST sequencer clock for sample phase
  	use SLOW sequencer clock for re-read
  	use FAST sequencer clock for readout

	Read out 10 APC128s: 5 'early' and 5 'late'
	
	Ireg = 000 1000 for DMILL

	Add 8 special events at end of readout. 25 CONVERTS PER SPECIAL 18.7.96
}